|
|
|
|
|
Petre Anghelescu
Pág. 73 - 78
This article presents an encryption system based on the PCA (Programmable Cellular Automata) theory and the implementation in reconfigurable hardware in order to achieve high speed communication for real time applications. The propose...
ver más
|
|
|
|
|
|
|
|
|
|
|
Vladislav Shatravin, Dmitriy Shashev and Stanislav Shidlovskiy
The remarkable results of applying machine learning algorithms to complex tasks are well known. They open wide opportunities in natural language processing, image recognition, and predictive analysis. However, their use in low-power intelligent systems i...
ver más
|
|
|
|
|
|
|
|
|
|
|
Wenjie Ma, Liuchang Zhuo, Luchu Li, Yuhao Liu and Hong Ren
In this paper, we study a reconfigurable intelligent surface (RIS)-aided multiuser MISO system with imperfect hardware, where the transceiver design is based on the statistical channel state information (CSI). Considering the transceiver hardware impairm...
ver más
|
|
|
|
|
|
|
|
|
|
|
Victor Bastidas, Johan Sebastián Eslava Garzón
Pág. 149 - 159
En este documento se presenta una metodología para el diseño de sistemas digitales usando reconfiguración parcial dinámica basada en diferencias en FPGA de la familia Spartan de Xilinx.Se aborda el problema de diseño en alto nivel de abstracción y se mue...
ver más
|
|
|
|
|
|
|
|
|
|
|
Alexey I. Dordopulo,Ilya I. Levin
Pág. 4 - 23
In the paper, we review a suboptimal methodology of mapping of a task information graph on the architecture of a reconfigurable computer system. Using performance reduction methods, we can solve computational problems which need hardware costs ...
ver más
|
|
|
|
|
|
|
|
|
|
|
Alexey I. Dordopulo,Ilya I. Levin
Pág. 4 - 23
In the paper, we review a suboptimal methodology of mapping of a task information graph on the architecture of a reconfigurable computer system. Using performance reduction methods, we can solve computational problems which need hardware costs ...
ver más
|
|
|
|
|
|
|
|
|
|
|
Hasan Irmak, Federico Corradi, Paul Detterer, Nikolaos Alachiotis and Daniel Ziener
This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Recon...
ver más
|
|
|
|
|
|
|
|
|
|
|
Jian Wang and Ying Li
Ensuring the security of IoT devices and chips at runtime has become an urgent task as they have been widely used in human life. Embedded memories are vital components of SoC (System on Chip) in these devices. If they are attacked or incur faults at runt...
ver más
|
|
|
|
|
|
|
|
|
|
|
Wael Deabes
This paper presents the hardware implementation of a stand-alone Electrical Capacitance Tomography (ECT) system employing a Field Programmable Gate Array (FPGA). The image reconstruction algorithms of the ECT system demand intensive computation and fast ...
ver más
|
|
|
|
|
|
|
|
|
|
|
Partha Sarathi Paul, Anurag Dhungel, Maisha Sadia, Md Razuan Hossain and Md Sakib Hasan
This paper presents a general method, called ?self-parameterization?, for designing one-dimensional (1-D) chaotic maps that provide wider chaotic regions compared to existing 1-D maps. A wide chaotic region is a desirable property, as it helps to provide...
ver más
|
|
|
|
|
|
|
|
|
|
|
Diba Das, Mehdi Hasan Chowdhury, Aditta Chowdhury, Kamrul Hasan, Quazi Delwar Hossain and Ray C. C. Cheung
The electrooculogram (EOG) is one of the most significant signals carrying eye movement information, such as blinks and saccades. There are many human?computer interface (HCI) applications based on eye blinks. For example, the detection of eye blinks can...
ver más
|
|
|
|
|
|
|
|
|
|
|
Iouliia Skliarova
It is well known that network-based parallel data processing algorithms are well suited to implementation in reconfigurable hardware recurring to either Field-Programmable Gate Arrays (FPGA) or Programmable Systems-on-Chip (PSoC). The intrinsic paralleli...
ver más
|
|
|
|
|
|
|
|
|
|
|
Sethakarn Prongnuch, Suchada Sitjongsataporn
Pág. 203 - 215
This paper introduces an analysis of Thai speech recognition for controlled car parking assist in the system-on-chip architecture. The objective is to investigate the male and female voice command signals, including Thai and English words, issued by the ...
ver más
|
|
|
|
|
|
|
|
|
|
|
Ahmad Abdo and Claude D?Amours
We propose an adaptive joint pre- and post-compensation to correct the filtering effects caused by cascading reconfigurable optical add drop multiplexers (ROADMs). The improvement is achieved without using additional hardware (HW) on the link or within t...
ver más
|
|
|
|
|
|
|
|
|
|
|
Mário P. Véstias
The convolutional neural network (CNN) is one of the most used deep learning models for image detection and classification, due to its high accuracy when compared to other machine learning algorithms. CNNs achieve better results at the cost of higher com...
ver más
|
|
|
|
|
|
|
|
|
|
|
Zümrüt Hatice SEKKELI, Ismail BAKAN
Pág. 203 - 220
The effect of technological developments, IoTs and Cyber-Physical Systems are begun to use at manufacturing. This alteration led to the start of the revolution Industry 4.0. (Wang and Zhou, 2015). In other words, the main elements of Industry...
ver más
|
|
|
|
|
|
|
|
|
|
|
Zehan Wang, Zhenggang Lu, Juyao Wei and Xiaojie Qiu
The virtual track train (VTT) is a new urban public transportation system that adopts all-axle steering and distributed drive. The Super autonomous Rail rapid Transit (SRT), as one of them, adopts a four-module six-axle structure. In response to its cruc...
ver más
|
|
|
|
|
|
|
|
|
|
|
Ye Chi, Haikun Liu, Ganwei Peng, Xiaofei Liao and Hai Jin
Non-volatile memories (NVMs) have aroused vast interest in hybrid memory systems due to their promising features of byte-addressability, high storage density, low cost per byte, and near-zero standby energy consumption. However, since NVMs have limited w...
ver más
|
|
|
|
|
|
|
|
|
|
|
Pedro Ponce, Omar Mata, Esteban Perez, Juan Roberto Lopez, Arturo Molina and Troy McDaniel
Since the COVID-19 Pandemic began, there have been several efforts to create new technology to mitigate the impact of the COVID-19 Pandemic around the world. One of those efforts is to design a new task force, robots, to deal with fundamental goals such ...
ver más
|
|
|
|
|
|
|
|
|
|
|
Tiago Gomes, Pedro Sousa, Miguel Silva, Mongkol Ekpanyapong and Sandro Pinto
In the new Internet of Things (IoT) era, embedded Field-Programmable Gate Array (FPGA) technology is enabling the deployment of custom-tailored embedded IoT solutions for handling different application requirements and workloads. Combined with the open R...
ver más
|
|
|
|
|
|